Applications for baseband signal processing face a fundamental tradeoff between computing accuracy and computing efficiency. On one hand, maximizing numerical accuracy improves the performance of the wireless connections and ease of implementing theoretical algorithms on real semiconductor devices. However, maintaining high numerical precision requires either/or wide data words and arithmetic logic units or complex representations like mantissa+exponent floating point representations that adversely affect computing efficiency.
The IEEE 754 floating point double precision standard is commonly used algorithm development, because it imposes very little precision loss due to representation. It is commonly implemented in general-purpose processors and some specialized processors such as DSPs and GPUs. The price of this sophistication is expensive computation, measured either by hardware costs (number of gates, area of semiconductor logic for implementation) or by power (energy per operation) relative to performance.
For example, representations of the IEEE Standard for Floating-Point Arithmetic (IEEE 754) which are commonly 32-bit for “single precision” and 64-bits for “double precision”, a complex number floating point multiply-add follows the below identified sequence of basic operations of for input A and B into an accumulator C.
1st operation) The input A real mantissa is multiplied with input B real mantissa, and the input A imaginary mantissa is multiplied with the input B imaginary mantissa. The input A real mantissa is multiplied with the input B imaginary mantissa. Finally, the input A imaginary mantissa is multiplied with the input B real mantissa.
2nd operation) The input A real exponent is added with the input B real exponent. The input A imaginary exponent is added with the input B imaginary exponent.
3rd operation) Compare the exponents. If sum of real exponents is smaller than the sum of imaginary exponents shift the product of real mantissa down by the difference in those sums, otherwise shift the product of imaginary exponents down by the difference in those sums, and subtract the mantissa products to form a real mantissa product. If the sum of input A real exponents plus input B imaginary exponents is smaller than the sum of the input A imaginary exponents plus input B real exponents, then a product of input A real mantissas and the input B imaginary mantissa is shifted down by a difference of the sums of the mantissa, otherwise shift the product of input A imaginary mantissa and the input B real mantissa down by the difference in the sum of the mantissas, and add the mantissa products to form the imaginary mantissa.
4th operation) Set the exponent for the real product to the greater of input A real plus input B real or input A imaginary plus input B imaginary. Set the exponent for the imaginary product to the greater of input A. real plus input B imaginary and input A imaginary plus input B real.
5th operation) Compare the exponent of the real product with the exponent of the accumulator C real. If the real product exponent is smaller than the accumulator, shift the product mantissa down by the difference between the exponent of the real product and the exponent of the accumulator; otherwise shift the accumulator C mantissa down by the difference. Next add the mantissas of the real product and the accumulator C. Select the larger exponent as a result exponent.
Compare the exponent of the imaginary product with exponent of the accumulator C imaginary. If the imaginary product exponent is smaller than the accumulator C shift the product mantissa down by the difference, else shift the accumulator mantissa down by the difference. Next add the mantissas of the imaginary product and the accumulator C. Select the larger exponent as a result exponent.
6th operation) Normalize the real mantissa by shifting up or down and adjust the real exponent by the amount of shift. Normalize the imaginary mantissa by shifting up or down and adjust the imaginary exponent by the amount of shift. Accordingly as is seen, to perform a multiply/add operation typically requires an operation sequence of multiply-shift-add-shift-add-shift-add on each component of a complex value.
As mentioned before, this sequence of operations have to be performed every time on complex numbers which affects the computing efficiency of the processing system. Accordingly what is needed is a system and method that addresses the above identified issues. The system and method must be easily implemented, adaptable and cost effective. The present invention addresses the above identified issues.